Guidelines for RF / Microwave Design -Layout Techniques and Strategies

Guidelines for RF / Microwave Design -Layout Techniques and Strategies

1.Low Level Analog, RF/Microwave and Digital Sections Must be Separated.

2.Divide RF/Microwave Section into Circuit Groups (VCO, LO, Amps, etc.).

3.Place High Frequency Components First, to Minimize Length of Each RF Route (Orientation for Function More Critical than DFM).

4.Place Highest Frequency Components Nearest Connectors.

5.Don’t Locate Unrelated Outputs and Inputs Near Each Other. Especially Multi-Stages Winding Back on One Another.

6.When Either the Output or Input to Amplifiers Must be Long, Choose the Output.

7.Remember, Trace Impedance (Zo) is a Critical Factor in the Effort to Control Reflections.

8.Impedance must Match Driver and Load.

9.In Traces Shorter than 1/20th λ Long, Zo Matching is Usually Not Important.

10.When Pull-up Resistors or Inductors are Used on the Outputs of Open Collector Devices, Place the Pull-up Component Right At the Output Pin it’s Pulling.

11.Also, make Certain to Decouple the Pull-up, in Addition to the Main Power Pins of the IC.

12.Inductors have Large Magnetic Fields Around Them-

*They Should Not be Placed Close Together,when In Parallel (Unless Intent is to have Their Magnetic Fields Couple).

*Separate Inductors by One(1) Times Body Height (Min) -(OR)-

*Place Perpendicular to One Another

13.Keep “ALL” Routes Confined to the Stage or Section to which they are Assigned-

*Digital Traces in the Digital Section. Period.

*Low Level Analog in Low Level Analog.

*RF / Microwave in RF / Microwave Section.

14.Don’t Route Traces into Adjoining Sections.

15.Short RF Traces should be on Component Side of Board, Routed to Eliminate Vias.

16.Next Layer Below RF Traces to be Ground.

17.Minimizing Vias in RF Path Minimizes Breaks in Ground Plane(s)-

--Minimizes Inductance.

--Helps Contain Stray Electric & Magnetic Fields.

18.Controls Lines can be Long, but Must Route Away from RF Inputs.

19.RF / Microwave Lines Must be Kept Away From One Another By Min Distances to Prevent Unintended Coupling & Crosstalk.

20.Minimum Spacing is a Function of How Much Coupling is Acceptable.

21.Equations in Wadell, Pages 181 - 254.

--Good for Crosstalk, Directional Couplers, Odd or Even Mode Coupled (Diff) Lines.

22.When Circuit MUST Loop Back on Itself and Outputs end up Near Inputs -

--Place Ground Copper (20 H Wide) Between Sections, Most specifically Between Inputs and Outputs.

--Use 20 H Wall if Copper is Less than 20 H Wide.

--Attach Ground Copper to Board Planes Every 1/20th Wavelength of Principal Frequency.

23.Use Same Methods when Unrelated Inputs and Outputs Must Be Near One Another.

24.In Multilayer Boards, When Signals Must Change layer, Route in Layer Pairs -

--Layer 1 Signals Reference Ground on Layer 2.

--When Direction Change Needed, Via Signal to Layer 3.

25.i.e.: First Four(4) Layers of a Board -

- - - - - - - - - - - Layer 1 (Signal - X Direction)

------------------- Layer 2 (Ground Plane)

- - - - - - - - - - - Layer 3 (Signal - Y Direction)

------------------- Layer 4 (Ground Plane)

26.Components Connecting to Ground -

--Flood Component Lead with Surface Ground.

(Let Soldermask or Mask Dam Define Pad).

--Ground Vias as Close to Component Lead as Possible. Preferably ON Component Lead.

--Multiple Vias (3, 4, etc.) Reduce Inductance and Help Eliminate Ground Bounce.

--Direct Connection. No Thermal Vias.

--Must attempt to permit Proper Solder Reflow

27.Ground: All Designs, 2 Layer or Multilayer -

--Unused Areas of Every Layer to be Poured with Ground Copper.

--Ground Copper and All Ground Planes through Board to be Connected with Vias Every 1/20th Wavelength Apart (Where Possible).

--Vias Closer than 1/20th λ are Better.

--Very Critical Circuits - Vias Closer than 1/ 20th λ Help Reduce Noise.

--Direct Connect Vias. NO Thermal Vias.

28.Ground:

--‘Copper Pours’ Too Small to have Vias Must be Removed (Can Act as Antenna).

--Arrange Poured Ground Around Signals to Completely Surround Signals -

--Ground Vias to Include Picket Fencing at Edge of Board. In Very Critical Circuits, Plate Board Edge.

--By Maintaining Isolation Between Circuits, Do Not Split Ground Plane.

--Attach Ground to Case Continuously.

--One Exception is Ground for Cable Shields.

29.Mismatched Source and Load Impedance:If Line can be λ/4 Long -

30.Mismatched Source and Load Impedance:If Line Can NOT be λ/4 Long -

31.Trace Corners -

Others Considered Fair to Good

32.‘T’-Junctions:

Ideal is the Wilkinson Splitter-

(What if Split to Load is Less than Critical Length?)

33.‘T’-Junctions (Acceptable):

34.Impedance of Vias

Wang, Taoyun, et al., “Quasi-static Analysis of a Microstrip Via Through a Hole in a Ground Plane,” IEEE Transactions on Microstrip Theory and Techniques, Vol.MTT-36, No. 6, June 1988, pp. 1007-1013.

35.Copper Patches can be placed Next to Signal Traces to Create Attachment Points for Wire or Solder to Create Tuning ‘C’ or ‘L’ -